/****************************************************************************
* 文件名: hRPWM.c
* 内容简述: hRPWM 驱动代码	
* 文件历史:
* 版本号	日期	作者	说明
*
*/

/* Includes ------------------------------------------------------------------*/
#include "main.h" 
//#include "hc32f3xx.h"
//#include "hc32f3xx_conf.h"
//#include "hc32_ll_hrpwm.h"
//#include "hc32_ll_gpio.h"
//#include "hc32_ll_def.h"
#include "hrtimer.h"
#include "Hrtim_debug.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/

#define SHADOW_ENABLE   1  //0:disable 1:enable
//#define HRPWM_COUNTERMODE_SELECT   HRPWM_COUNTERMODE_UP
#define SDK_ENABLE      1
/***************************IDLE configuration end****************************/

void ExternEventConfig(void);
//void Hrtim_Interrupt_Confi(void);
//void TMR6_IrqHandler(void);
//void HRTIM_Repetive_config(uint16_t select_mode,uint32_t repetive_num);
//void HWSynchRunConfi(uint32_t modeselt);
void HRTIM_IDLE_Conf(void);
void HRPWM_EMB_Conf(void);
void HRTIM_BM_Conf(void);
//__STATIC_INLINE void HRPWM_Buf_SetUnitGlobalFlagSrc(CM_HRPWM_TypeDef *HRPWMx, uint32_t u32Src);
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Extern variables ----------------------------------------------------------*/
//LL_Ctrl  LL_Ctrl_Real = 
//{
//	PERIOD_VALUE,
//	
//	0,
//	0,
//	PERIOD_VALUE,
//	
//	0,
//	0,
//	PERIOD_VALUE,		
//};
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

//gpio enable-function as PWM configuration----CHyang
void GPIO_LLC_HB_outputs_Config(void)
{
    GPIO_HrpwmPinCmd(HRPWM_1A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_1B_PIN, ENABLE);
	  GPIO_HrpwmPinCmd(HRPWM_2A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_2B_PIN, ENABLE);
		GPIO_HrpwmPinCmd(HRPWM_3A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_3B_PIN, ENABLE);
		GPIO_HrpwmPinCmd(HRPWM_4A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_4B_PIN, ENABLE);
		GPIO_HrpwmPinCmd(HRPWM_5A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_5B_PIN, ENABLE);
		GPIO_HrpwmPinCmd(HRPWM_6A_PIN, ENABLE);
    GPIO_HrpwmPinCmd(HRPWM_6B_PIN, ENABLE);
}
#if 0
/***********************************************************
*function name:
*descrition:
*para:
*return:
************************************************************/
void trim(void)
{
  int TRIMVOL;
  int TRIMSEL=128;
	WRITE_REG32(CM_HRPWM1->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM1->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM1->HRPWM_TECTLRCALCR,1<<17);
	
	WRITE_REG32(CM_HRPWM2->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM2->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM2->HRPWM_TECTLRCALCR,1<<17);
	
	WRITE_REG32(CM_HRPWM3->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM3->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM3->HRPWM_TECTLRCALCR,1<<17);
	
	
	WRITE_REG32(CM_HRPWM4->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM4->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM4->HRPWM_TECTLRCALCR,1<<17);
	
	WRITE_REG32(CM_HRPWM5->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM5->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM5->HRPWM_TECTLRCALCR,1<<17);
	
	
	WRITE_REG32(CM_HRPWM6->HRPWM_TECTLRCALCR,(TRIMVOL<<8)+TRIMSEL);     
  SET_REG32_BIT(CM_HRPWM6->HRPWM_TECTLRCALCR,1<<16);
	SET_REG32_BIT(CM_HRPWM6->HRPWM_TECTLRCALCR,1<<17);
}
#endif
/*****************************************函数*********************************************************/
/*******************************************************************************************************
** function name: HRTIM_Config()
** description  ：HRPWM configuration
**  
** 
**   
*******************************************************************************************************/
 void HRTIM_Config(void)
{
	 stc_hrpwm_init_t stcHrpwmInit;
   stc_hrpwm_pwm_init_t stchrpwmpwminit;
	 stc_hrpwm_deadtime_config_t stchrpwmdeadtimeconfig;
	 stc_hrpwm_buf_config_t pstcBufConfig;
	 stc_hrpwm_ph_config_t pstcPHConfig;
	 //stc_hrpwm_phase_match_config_t stcPhaseConfig;    
	
	 //step1.enable PWM CLK
	 FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_HRPWM_1 | FCG2_PERIPH_HRPWM_2 | FCG2_PERIPH_HRPWM_3 |
	                        FCG2_PERIPH_HRPWM_4 | FCG2_PERIPH_HRPWM_5 | FCG2_PERIPH_HRPWM_6 , ENABLE);

	 //step2.PWM pin map select,do not used here
	 //SET_REG32_BIT(CM_HRPWM1->GCTLR, (1<<15));
	
	 //step3.default configuration
   HRPWM_DeInit(HRPWM_UNIT_1);
	 HRPWM_DeInit(HRPWM_UNIT_2);
	 HRPWM_DeInit(HRPWM_UNIT_3);
	 HRPWM_DeInit(HRPWM_UNIT_4);
	 HRPWM_DeInit(HRPWM_UNIT_5);
	 HRPWM_DeInit(HRPWM_UNIT_6);
	
   //step3.hrpwm calibration and enable hrpwm
	 /* Calibrate process */
    if (LL_OK != HRPWM_CALIB_ProcessSingle()) 
		{
			
    }
		//trim();//???,not found resgiter here.
			
		/* HRPWM function enable */
		HRPWM_Enable(CM_HRPWM1);
		HRPWM_Enable(CM_HRPWM2);
		HRPWM_Enable(CM_HRPWM3);
		HRPWM_Enable(CM_HRPWM4);
		HRPWM_Enable(CM_HRPWM5);
		HRPWM_Enable(CM_HRPWM6);
//		
//		HRPWM_Disable(CM_HRPWM1);
//		HRPWM_Disable(CM_HRPWM2);
//		HRPWM_Disable(CM_HRPWM3);
//		HRPWM_Disable(CM_HRPWM4);
//		HRPWM_Disable(CM_HRPWM5);
//		HRPWM_Disable(CM_HRPWM6);
			

    /* Count function initialize */
		HRPWM_StructInit(&stcHrpwmInit);
		#if HRPWM_COUNTERMODE_SELECT == HRPWM_COUNTERMODE_UPDOWN
    stcHrpwmInit.u32CountMode = HRPWM_MD_TRIANGLE;
		#else
		stcHrpwmInit.u32CountMode = HRPWM_MD_SAWTOOTH;
		#endif
    stcHrpwmInit.u32PeriodValue = PERIOD_VALUE;//up mode ,must set this value.
		stcHrpwmInit.u32CountReload = HRPWM_CNT_RELOAD_ON;//continue counter mode

    (void)HRPWM_Init(HRPWM_UNIT_1, &stcHrpwmInit);
	  (void)HRPWM_Init(HRPWM_UNIT_2, &stcHrpwmInit);
		(void)HRPWM_Init(HRPWM_UNIT_3, &stcHrpwmInit);		
		(void)HRPWM_Init(HRPWM_UNIT_4, &stcHrpwmInit);
		(void)HRPWM_Init(HRPWM_UNIT_5, &stcHrpwmInit);
		(void)HRPWM_Init(HRPWM_UNIT_6, &stcHrpwmInit);
    /* PWM initialize-LLC_PHASE1 + LLC_PHASE2*/
		  
#if HRPWM_COUNTERMODE_SELECT == HRPWM_COUNTERMODE_UPDOWN
 
		/***********************************UINT1****************************/
		/***********************************UNIT1 A**************************/
	
#else


		/***********************************UINT1****************************/
		/***********************************UNIT1 A**************************/
		//PCNAR1
		//stchrpwmpwminit.u32CompareValue = 0;	
    HRPWM_PWM_StructInit(&stchrpwmpwminit);
		
		stchrpwmpwminit.u32StopPolarity      				= HRPWM_PWM_STOP_LOW;
		stchrpwmpwminit.u32StartPolarity     				= HRPWM_PWM_START_LOW;
		
		stchrpwmpwminit.u32PeakPolarity      				= HRPWM_PWM_PEAK_HOLD;
		stchrpwmpwminit.u32ValleyPolarity    				= HRPWM_PWM_VALLEY_HIGH;
		
		stchrpwmpwminit.u32UpMatchAPolarity   			= HRPWM_PWM_UP_MATCH_A_LOW;
		stchrpwmpwminit.u32DownMatchAPolarity 			= HRPWM_PWM_DOWN_MATCH_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchBPolarity         = HRPWM_PWM_UP_MATCH_B_HOLD;
		stchrpwmpwminit.u32DownMatchBPolarity       = HRPWM_PWM_DOWN_MATCH_B_HOLD;
		
		stchrpwmpwminit.u32UpMatchEPolarity         = HRPWM_PWM_UP_MATCH_E_HOLD;
		stchrpwmpwminit.u32DownMatchEPolarity       = HRPWM_PWM_DOWN_MATCH_E_HOLD;
		
		stchrpwmpwminit.u32UpMatchFPolarity         = HRPWM_PWM_UP_MATCH_F_HOLD;    
		stchrpwmpwminit.u32DownMatchFPolarity       = HRPWM_PWM_DOWN_MATCH_F_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialAPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_A_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialAPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialBPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_B_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialBPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_B_HOLD;
				
		HRPWM_PWM_ChAInit(CM_HRPWM1, &stchrpwmpwminit);
		//HRPWM_PWM_ChAInit(CM_HRPWM2, &stchrpwmpwminit);
		//HRPWM_PWM_ChAInit(CM_HRPWM3, &stchrpwmpwminit);
		HRPWM_PWM_ChAInit(CM_HRPWM6, &stchrpwmpwminit);
		//HRPWM_PWM_ChAInit(CM_HRPWM5, &stchrpwmpwminit);
		//HRPWM_PWM_ChAInit(CM_HRPWM6, &stchrpwmpwminit);
		
		
				//PCNAR1
		//stchrpwmpwminit.u32CompareValue = 0;		
		stchrpwmpwminit.u32StopPolarity      				= HRPWM_PWM_STOP_LOW;
		stchrpwmpwminit.u32StartPolarity     				= HRPWM_PWM_START_LOW;
		
		stchrpwmpwminit.u32PeakPolarity      				= HRPWM_PWM_PEAK_HOLD;
		stchrpwmpwminit.u32ValleyPolarity    				= HRPWM_PWM_VALLEY_LOW;
		
		stchrpwmpwminit.u32UpMatchAPolarity   			= HRPWM_PWM_UP_MATCH_A_HIGH;
		stchrpwmpwminit.u32DownMatchAPolarity 			= HRPWM_PWM_DOWN_MATCH_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchBPolarity         = HRPWM_PWM_UP_MATCH_B_HOLD;
		stchrpwmpwminit.u32DownMatchBPolarity       = HRPWM_PWM_DOWN_MATCH_B_HOLD;
		
		stchrpwmpwminit.u32UpMatchEPolarity         = HRPWM_PWM_UP_MATCH_E_HOLD;
		stchrpwmpwminit.u32DownMatchEPolarity       = HRPWM_PWM_DOWN_MATCH_E_HOLD;
		
		stchrpwmpwminit.u32UpMatchFPolarity         = HRPWM_PWM_UP_MATCH_F_HOLD;    
		stchrpwmpwminit.u32DownMatchFPolarity       = HRPWM_PWM_DOWN_MATCH_F_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialAPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_A_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialAPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialBPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_B_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialBPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_B_HOLD;
		

		HRPWM_PWM_ChAInit(CM_HRPWM2, &stchrpwmpwminit);
		HRPWM_PWM_ChAInit(CM_HRPWM5, &stchrpwmpwminit);

		//SR
		stchrpwmpwminit.u32StopPolarity      				= HRPWM_PWM_STOP_LOW;
		stchrpwmpwminit.u32StartPolarity     				= HRPWM_PWM_START_LOW;
		
		stchrpwmpwminit.u32PeakPolarity      				= HRPWM_PWM_PEAK_HOLD;
		stchrpwmpwminit.u32ValleyPolarity    				= HRPWM_PWM_VALLEY_HOLD;
		
		stchrpwmpwminit.u32UpMatchAPolarity   			= HRPWM_PWM_UP_MATCH_A_LOW;
		stchrpwmpwminit.u32DownMatchAPolarity 			= HRPWM_PWM_DOWN_MATCH_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchBPolarity         = HRPWM_PWM_UP_MATCH_B_HOLD;
		stchrpwmpwminit.u32DownMatchBPolarity       = HRPWM_PWM_DOWN_MATCH_B_HOLD;
		
		stchrpwmpwminit.u32UpMatchEPolarity         = HRPWM_PWM_UP_MATCH_E_HIGH;
		stchrpwmpwminit.u32DownMatchEPolarity       = HRPWM_PWM_DOWN_MATCH_E_HOLD;
		
		stchrpwmpwminit.u32UpMatchFPolarity         = HRPWM_PWM_UP_MATCH_F_HOLD;    
		stchrpwmpwminit.u32DownMatchFPolarity       = HRPWM_PWM_DOWN_MATCH_F_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialAPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_A_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialAPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialBPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_B_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialBPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_B_HOLD;
		
		HRPWM_PWM_ChAInit(CM_HRPWM4, &stchrpwmpwminit);
		HRPWM_PWM_ChBInit(CM_HRPWM3, &stchrpwmpwminit);
		
		stchrpwmpwminit.u32StopPolarity      				= HRPWM_PWM_STOP_LOW;
		stchrpwmpwminit.u32StartPolarity     				= HRPWM_PWM_START_LOW;
		
		stchrpwmpwminit.u32PeakPolarity      				= HRPWM_PWM_PEAK_LOW;
		stchrpwmpwminit.u32ValleyPolarity    				= HRPWM_PWM_VALLEY_LOW;
		
		stchrpwmpwminit.u32UpMatchAPolarity   			= HRPWM_PWM_UP_MATCH_A_HOLD;
		stchrpwmpwminit.u32DownMatchAPolarity 			= HRPWM_PWM_DOWN_MATCH_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchBPolarity         = HRPWM_PWM_UP_MATCH_B_LOW;
		stchrpwmpwminit.u32DownMatchBPolarity       = HRPWM_PWM_DOWN_MATCH_B_HOLD;
		
		stchrpwmpwminit.u32UpMatchEPolarity         = HRPWM_PWM_UP_MATCH_E_HOLD;
		stchrpwmpwminit.u32DownMatchEPolarity       = HRPWM_PWM_DOWN_MATCH_E_HOLD;
		
		stchrpwmpwminit.u32UpMatchFPolarity         = HRPWM_PWM_UP_MATCH_F_HIGH;    
		stchrpwmpwminit.u32DownMatchFPolarity       = HRPWM_PWM_DOWN_MATCH_F_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialAPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_A_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialAPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_A_HOLD;
		
		stchrpwmpwminit.u32UpMatchSpecialBPolarity  = HRPWM_PWM_UP_MATCH_SPECIAL_B_HOLD;
		stchrpwmpwminit.u32DownMatchSpecialBPolarity= HRPWM_PWM_DOWN_MATCH_SPECIAL_B_HOLD;

    HRPWM_PWM_ChBInit(CM_HRPWM4, &stchrpwmpwminit);
		HRPWM_PWM_ChAInit(CM_HRPWM3, &stchrpwmpwminit);
#endif		
		
		
		/************************************************************************/
    /***************UNIT1********************/
	  //PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_1, (UINT1_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_1, (UINT1_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_1, (UINT1_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_1, (UINT1_CMPAC_VALUE));//HRPWM_CMP_REG_A
		
		//SCMPA		
		HRPWM_SetSpecialCompareAValue(HRPWM_UNIT_1, (UINT1_PRD_VALUE >> 2));
		HRPWM_SetSpecialCompareAValue_Buf(HRPWM_UNIT_1, (UINT1_PRD_VALUE >> 2));//HRPWM_CMP_REG_A
		
		
		/***************UNIT2********************/
		//PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_2, (UINT2_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_2, (UINT2_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_2, (UINT2_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_2, (UINT2_CMPAC_VALUE));//HRPWM_CMP_REG_A

		/***************UNIT3********************/
    //PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_3, (UINT3_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_3, (UINT3_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_3, (UINT3_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_3, (UINT3_CMPAC_VALUE));//HRPWM_CMP_REG_A
    //CMPB/D
		HRPWM_SetCompareBValue(HRPWM_UNIT_3, (UINT3_CMPBD_VALUE));
		HRPWM_SetCompareBValue_Buf(HRPWM_UNIT_3, (UINT3_CMPBD_VALUE));//HRPWM_CMP_REG_A
		//CMPE/G
		HRPWM_SetCompareEValue(HRPWM_UNIT_3, (UINT3_CMPEG_VALUE));
		HRPWM_SetCompareEValue_Buf(HRPWM_UNIT_3, (UINT3_CMPEG_VALUE));//HRPWM_CMP_REG_A
    //CMPF/I
		HRPWM_SetCompareFValue(HRPWM_UNIT_3, (UINT3_CMPFH_VALUE));
		HRPWM_SetCompareFValue_Buf(HRPWM_UNIT_3, (UINT3_CMPFH_VALUE));//HRPWM_CMP_REG_A
		
		/***************UNIT4********************/
	  //PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_6, (UINT4_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_6, (UINT4_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_6, (UINT4_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_6, (UINT4_CMPAC_VALUE));//HRPWM_CMP_REG_A
		
		/***************UNIT5********************/
		//PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_5, (UINT5_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_5, (UINT5_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_5, (UINT5_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_5, (UINT5_CMPAC_VALUE));//HRPWM_CMP_REG_A

		/***************UNIT6********************/
    //PRDA/B
    HRPWM_SetPeriodValue(HRPWM_UNIT_4, (UINT6_PRD_VALUE));//
	  HRPWM_SetPeriodValue_Buf(HRPWM_UNIT_4, (UINT6_PRD_VALUE));//
		//CMPA/C
		HRPWM_SetCompareAValue(HRPWM_UNIT_4, (UINT6_CMPAC_VALUE));
		HRPWM_SetCompareAValue_Buf(HRPWM_UNIT_4, (UINT6_CMPAC_VALUE));//HRPWM_CMP_REG_A
    //CMPB/D
		HRPWM_SetCompareBValue(HRPWM_UNIT_4, (UINT6_CMPBD_VALUE));
		HRPWM_SetCompareBValue_Buf(HRPWM_UNIT_4, (UINT6_CMPBD_VALUE));//HRPWM_CMP_REG_A
		//CMPE/G
		HRPWM_SetCompareEValue(HRPWM_UNIT_4, (UINT6_CMPEG_VALUE));
		HRPWM_SetCompareEValue_Buf(HRPWM_UNIT_4, (UINT6_CMPEG_VALUE));//HRPWM_CMP_REG_A
    //CMPF/I
		HRPWM_SetCompareFValue(HRPWM_UNIT_4, (UINT6_CMPFH_VALUE));
		HRPWM_SetCompareFValue_Buf(HRPWM_UNIT_4, (UINT6_CMPFH_VALUE));//HRPWM_CMP_REG_A


		/***************Dead time configuration ********************/
		/***********************unit1*******************************/
		HRPWM_DeadTimeStructInit(&stchrpwmdeadtimeconfig);
    stchrpwmdeadtimeconfig.u32EqualUpDown = HRPWM_DEADTIME_EQUAL_ON;  //dead time DTU = DTD
		stchrpwmdeadtimeconfig.u32BufUp       = HRPWM_DEADTIME_CNT_UP_BUF_ON;  //enable shadown
		stchrpwmdeadtimeconfig.u32BufDown     = HRPWM_DEADTIME_CNT_DOWN_BUF_ON;  //enable shadown
		HRPWM_DeadTimeConfig(HRPWM_UNIT_1, &stchrpwmdeadtimeconfig);
		
		
		//deadtime vaule configuration
		HRPWM_SetDeadTimeUpValue(HRPWM_UNIT_1,UINT1_DT_UP_VALUE);
		HRPWM_SetDeadTimeUpValue_Buf(HRPWM_UNIT_1,UINT1_DT_UP_VALUE);
    HRPWM_SetDeadTimeDownValue(HRPWM_UNIT_1, UINT1_DT_DOWN_VALUE);
		HRPWM_SetDeadTimeDownValue_Buf(HRPWM_UNIT_1, UINT1_DT_DOWN_VALUE);
		
    HRPWM_DeadTimeEnable(HRPWM_UNIT_1);//enable Dead time
		
		/***********************unit2*******************************/
	  stchrpwmdeadtimeconfig.u32EqualUpDown = HRPWM_DEADTIME_EQUAL_ON;  //dead time DTU = DTD
		stchrpwmdeadtimeconfig.u32BufUp       = HRPWM_DEADTIME_CNT_UP_BUF_ON;  //enable shadown
		stchrpwmdeadtimeconfig.u32BufDown     = HRPWM_DEADTIME_CNT_DOWN_BUF_ON;  //enable shadown
		HRPWM_DeadTimeConfig(HRPWM_UNIT_2, &stchrpwmdeadtimeconfig);
		
		
		HRPWM_SetDeadTimeUpValue(HRPWM_UNIT_2,UINT1_DT_UP_VALUE);
		HRPWM_SetDeadTimeUpValue_Buf(HRPWM_UNIT_2,UINT1_DT_UP_VALUE);
    HRPWM_SetDeadTimeDownValue(HRPWM_UNIT_2, UINT1_DT_DOWN_VALUE);
		HRPWM_SetDeadTimeDownValue_Buf(HRPWM_UNIT_2, UINT1_DT_DOWN_VALUE);
		
    HRPWM_DeadTimeEnable(HRPWM_UNIT_2);
		
		/***********************unit4*******************************/
	  stchrpwmdeadtimeconfig.u32EqualUpDown = HRPWM_DEADTIME_EQUAL_ON;  //dead time DTU = DTD
		stchrpwmdeadtimeconfig.u32BufUp       = HRPWM_DEADTIME_CNT_UP_BUF_ON;  //enable shadown
		stchrpwmdeadtimeconfig.u32BufDown     = HRPWM_DEADTIME_CNT_DOWN_BUF_ON;  //enable shadown
		HRPWM_DeadTimeConfig(HRPWM_UNIT_6, &stchrpwmdeadtimeconfig);

		HRPWM_SetDeadTimeUpValue(HRPWM_UNIT_6,UINT1_DT_UP_VALUE);
		HRPWM_SetDeadTimeUpValue_Buf(HRPWM_UNIT_6,UINT1_DT_UP_VALUE);
    HRPWM_SetDeadTimeDownValue(HRPWM_UNIT_6, UINT1_DT_DOWN_VALUE);
		HRPWM_SetDeadTimeDownValue_Buf(HRPWM_UNIT_6, UINT1_DT_DOWN_VALUE);
		
    HRPWM_DeadTimeEnable(HRPWM_UNIT_6);
		
		/***********************unit5*******************************/
		stchrpwmdeadtimeconfig.u32EqualUpDown = HRPWM_DEADTIME_EQUAL_ON;  //dead time DTU = DTD
		stchrpwmdeadtimeconfig.u32BufUp       = HRPWM_DEADTIME_CNT_UP_BUF_ON;  //enable shadown
		stchrpwmdeadtimeconfig.u32BufDown     = HRPWM_DEADTIME_CNT_DOWN_BUF_ON;  //enable shadown
		HRPWM_DeadTimeConfig(HRPWM_UNIT_5, &stchrpwmdeadtimeconfig);
		
		HRPWM_SetDeadTimeUpValue(HRPWM_UNIT_5,UINT1_DT_UP_VALUE);
		HRPWM_SetDeadTimeUpValue_Buf(HRPWM_UNIT_5,UINT1_DT_UP_VALUE);
    HRPWM_SetDeadTimeDownValue(HRPWM_UNIT_5, UINT1_DT_DOWN_VALUE);
		HRPWM_SetDeadTimeDownValue_Buf(HRPWM_UNIT_5, UINT1_DT_DOWN_VALUE);
		
    HRPWM_DeadTimeEnable(HRPWM_UNIT_5);

	
		/***************shadown configuration ***********************************************************/
		HRPWM_BufStructInit(&pstcBufConfig);
		//select single shadown
		pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_PEAK;
		pstcBufConfig.enBufTransU1Single      = ENABLE;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
		//pstcBufConfig.enBufTransU1Single = HRPWM_BUF_TRANS1_VALLEY;
		//period 
		HRPWM_PeriodBufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM1);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM1);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM1);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM1);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM1);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM1,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM1);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM1);
		
		//phase 
		//HRPWM_Buf_PhaseSetCond(HRPWM_BUF_TRANS1_VALLEY);
    HRPWM_PH_BufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT1);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM1, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);

		
//		SET_REG32_BIT(CM_HRPWM1->GBCONR, (((uint32_t)1)<<HRPWM_GBCONR_OSTENU1_POS ) );//单元1单次周期点缓存功能使能
//		//signal shadow		
//		SET_REG32_BIT(CM_HRPWM1->GCONR1, (4 << 20));
		
    /******************************unit2*************************************/
    //select single shadown after U1
		pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_INVD;
		pstcBufConfig.enBufTransU1Single      = ENABLE ;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
		//period 
		//period 
		HRPWM_PeriodBufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM2);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM2);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM2);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM2);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM2);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM2,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM2);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM2);
		
		//phase 
//		HRPWM_Buf_PhaseSetCond(&pstcBufConfig);
//    HRPWM_Buf_PhaseBufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT2);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM2, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);
    /******************************unit3*************************************/
		
    pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_INVD;
		pstcBufConfig.enBufTransU1Single      = ENABLE ;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
				//period 
		HRPWM_PeriodBufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM3);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM3);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM3);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM3);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM3);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM3,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM3);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM3);
		
		//phase 
//		HRPWM_Buf_PhaseSetCond(&pstcBufConfig);
//    HRPWM_Buf_PhaseBufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT3);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM3, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);		

    /******************************unit4*************************************/
    //select single shadown after U1
		pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_INVD;
		pstcBufConfig.enBufTransU1Single      = ENABLE;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
				//period 
		HRPWM_PeriodBufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM4);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM4);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM4);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM4);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM4);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM4,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM4);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM4);
		
		//phase 
//		HRPWM_Buf_PhaseSetCond(&pstcBufConfig);
//    HRPWM_Buf_PhaseBufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT4);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM4, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);		

    /******************************unit5*************************************/
    //select single shadown after U1
		pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_INVD;
		pstcBufConfig.enBufTransU1Single      = ENABLE;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
				//period 
		HRPWM_PeriodBufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM5);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM5);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM5);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM5);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM5);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM5,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM5);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM5);
		
		//phase 
//		HRPWM_Buf_PhaseSetCond(&pstcBufConfig);
//    HRPWM_Buf_PhaseBufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT5);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM5, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);		

   /******************************unit6*************************************/
    //select single shadown after U1
		pstcBufConfig.u32BufTransCond         = HRPWM_BUF_TRANS_INVD;
		pstcBufConfig.enBufTransU1Single      = ENABLE ;
		pstcBufConfig.enBufTransAfterU1Single = DISABLE;
				//period 
		HRPWM_PeriodBufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_PeriodBufEnable(CM_HRPWM6);
		//CMPAE
    HRPWM_GeneralAEBufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_GeneralAEBufEnable(CM_HRPWM6);
		//CMPBF
		HRPWM_GeneralBFBufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_GeneralBFBufEnable(CM_HRPWM6);
		//SCMPA
		HRPWM_SpecialABufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_SpecialABufEnable(CM_HRPWM6);
		//SCMPB
		HRPWM_SpecialBBufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_SpecialBBufEnable(CM_HRPWM6);
		//control register 
//		HRPWM_Buf_ControlRegConfig(&pstcBufConfig);
//		HRPWM_Buf_ControlRegEnable(CM_HRPWM1);
		//dead time 
		HRPWM_DeadTimeBufConfig(CM_HRPWM6,&pstcBufConfig);
		HRPWM_DeadTimeUpBufEnable(CM_HRPWM6);
		HRPWM_DeadTimeDownBufEnable(CM_HRPWM6);
		
		//phase 
//		HRPWM_Buf_PhaseSetCond(&pstcBufConfig);
//    HRPWM_Buf_PhaseBufEnable();
		
		//global shadown enable
		HRPWM_UnitGlobalBufEnable(HRPWM_UNIT6);
		//global shadown enable flag set
		HRPWM_SetUnitGlobalBufFlagSrc(CM_HRPWM6, HRPWM_GLOBAL_BUF_SRC_U1_SINGLE);		

   /*******************phase configuration******************************/
	 HRPWM_PH_StructInit(&pstcPHConfig);
		//P1_2A configuration	
		HRPWM_PH_SetCompareValue(HRPWM_PH_MATCH_IDX1, UINT1_PHASE_1);
    HRPWM_PH_SetCompareValue_Buf(HRPWM_PH_MATCH_IDX1, UINT1_PHASE_1);
		pstcPHConfig.u32PhaseIndex = HRPWM_PH_MATCH_IDX1;
		pstcPHConfig.u32ForceChA   = HRPWM_PH_MATCH_FORCE_CHA_OFF;
		HRPWM_PH_Config(HRPWM_UNIT_5, &pstcPHConfig);
    HRPWM_PH_Enable(HRPWM_UNIT_5);

		
		//P1_SR configuration		
		HRPWM_PH_SetCompareValue(HRPWM_PH_MATCH_IDX2, UINT1_PHASE_2);
    HRPWM_PH_SetCompareValue_Buf(HRPWM_PH_MATCH_IDX2, UINT1_PHASE_2);
		pstcPHConfig.u32PhaseIndex = HRPWM_PH_MATCH_IDX2;
		pstcPHConfig.u32ForceChA   = HRPWM_PH_MATCH_FORCE_CHA_OFF;
		pstcPHConfig.u32ForceChB   = HRPWM_PH_MATCH_FORCE_CHB_OFF;
		HRPWM_PH_Config(HRPWM_UNIT_3, &pstcPHConfig);
    HRPWM_PH_Enable(HRPWM_UNIT_3);

		
		//P2_2A configuration    
		HRPWM_PH_SetCompareValue(HRPWM_PH_MATCH_IDX3, UINT1_PHASE_3);
    HRPWM_PH_SetCompareValue_Buf(HRPWM_PH_MATCH_IDX3, UINT1_PHASE_3);
		pstcPHConfig.u32PhaseIndex = HRPWM_PH_MATCH_IDX3;
		pstcPHConfig.u32ForceChA   = HRPWM_PH_MATCH_FORCE_CHA_OFF;
		HRPWM_PH_Config(HRPWM_UNIT_6, &pstcPHConfig);
    HRPWM_PH_Enable(HRPWM_UNIT_6);
		
		
		//P2_2B configuration
    HRPWM_PH_SetCompareValue(HRPWM_PH_MATCH_IDX4, UINT1_PHASE_4);
    HRPWM_PH_SetCompareValue_Buf(HRPWM_PH_MATCH_IDX4, UINT1_PHASE_4);
		pstcPHConfig.u32PhaseIndex = HRPWM_PH_MATCH_IDX4;
		pstcPHConfig.u32ForceChA   = HRPWM_PH_MATCH_FORCE_CHA_OFF;
		HRPWM_PH_Config(HRPWM_UNIT_2, &pstcPHConfig);
    HRPWM_PH_Enable(HRPWM_UNIT_2);

		
			//P2_SR configuration
		HRPWM_PH_SetCompareValue(HRPWM_PH_MATCH_IDX5, UINT1_PHASE_5);
    HRPWM_PH_SetCompareValue_Buf(HRPWM_PH_MATCH_IDX5, UINT1_PHASE_5);
		pstcPHConfig.u32PhaseIndex = HRPWM_PH_MATCH_IDX5;
		pstcPHConfig.u32ForceChA   = HRPWM_PH_MATCH_FORCE_CHA_OFF;
		pstcPHConfig.u32ForceChB   = HRPWM_PH_MATCH_FORCE_CHB_OFF;
		HRPWM_PH_Config(HRPWM_UNIT_4, &pstcPHConfig);
    HRPWM_PH_Enable(HRPWM_UNIT_4);

	
    /******************************软件触发缓存使能*********************************************/
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT1);
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT2);
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT3);
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT4);
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT5);
		HRPWM_UnitSWBufTrigger(HRPWM_UNIT6);
		
		//SCMPA direction
    HRPWM_MatchSpecialEventEnable(CM_HRPWM1,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM1,HRPWM_EVT_UP_MATCH_SPECIAL_B);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM2,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM2,HRPWM_EVT_UP_MATCH_SPECIAL_B);
    HRPWM_MatchSpecialEventEnable(CM_HRPWM3,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM3,HRPWM_EVT_UP_MATCH_SPECIAL_B);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM4,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM4,HRPWM_EVT_UP_MATCH_SPECIAL_B);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM5,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM5,HRPWM_EVT_UP_MATCH_SPECIAL_B);
    HRPWM_MatchSpecialEventEnable(CM_HRPWM6,HRPWM_EVT_UP_MATCH_SPECIAL_A);
		HRPWM_MatchSpecialEventEnable(CM_HRPWM6,HRPWM_EVT_UP_MATCH_SPECIAL_B);
		
		//external event configuration
		//ExternEventConfig();
		
    //IDLE configuration
		HRTIM_IDLE_Conf();
		
		//
		HRTIM_BM_Conf();
		
		//EMB configuration
		HRPWM_EMB_Conf();

   //interrupr configuration
	 //Hrtim_Interrupt_Confi();
	
	 // PWM output command 
    HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_1);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_1);
		
		HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_2);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_2);
		
		HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_3);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_3);
		
		HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_4);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_4);
		
		HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_5);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_5);
		
		HRPWM_PWM_ChAOutputEnable(HRPWM_UNIT_6);
		HRPWM_PWM_ChBOutputEnable(HRPWM_UNIT_6);
	 
	  //UINITx shadown enable
	  HRPWM_UnitGlobalBufEnable(HRPWM_UNIT_ALL);
	  //enable one shot mode
	  HRPWM_U1SingleTransBufConfig(HRPWM_BUF_U1_SINGLE_TRANS_ON);
	  //trigger one shot
	  HRPWM_U1SingleTransBufTrigger();
	 
	  //
//	  HRPWM_Idle_Exit(HRPWM_SW_SYNC_UNIT_ALL,HRPWM_SW_SYNC_CH_A);
//	  HRPWM_Idle_Exit(HRPWM_SW_SYNC_UNIT_ALL,HRPWM_SW_SYNC_CH_B);
	  
	  //software sync run
	  HRPWM_SWSyncStart(HRPWM_UNIT_ALL);
		
		
}


/**************************************************************
* @brief  IDLE configuration
*         IDLE mode congfiguration
*        
* @param  none
* @retval none
***************************************************************/
void HRTIM_IDLE_Conf(void)
{
	  stc_hrpwm_idle_delay_init_t  pstcIdleDelayInit;
	
	  HRPWM_IDLE_DELAY_StructInit(&pstcIdleDelayInit);
	  //delay idle select 
		pstcIdleDelayInit.u32IdleOutputChAStatus = HRPWM_IDLE_OUTPUT_CHA_ON;    //IDLE enable  
		pstcIdleDelayInit.u32IdleOutputChBStatus = HRPWM_IDLE_OUTPUT_CHB_ON;    //IDLE enable
	  pstcIdleDelayInit.u32PeriodPoint         = HRPWM_CPLT_PERIOD_SAWTOOTH_PEAK_TRIANGLE_VALLEY;
		pstcIdleDelayInit.u32TriggerSrc = HRPWM_IDLE_DELAY_TRIG_SW;             //IDLE trig source
		
	  
    HRPWM_IDLE_DELAY_Init(CM_HRPWM1, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM1, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM1, HRPWM_IDLE_CHA_LVL_LOW);
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM1);                                   //enbale delay idle	
	
    HRPWM_IDLE_DELAY_Init(CM_HRPWM2, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM2, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM2, HRPWM_IDLE_CHA_LVL_LOW);
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM2);                                   //enbale delay idle
		
	  HRPWM_IDLE_DELAY_Init(CM_HRPWM3, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM3, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM3, HRPWM_IDLE_CHA_LVL_LOW);		
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM3);                                   //enbale delay idle	
	
    HRPWM_IDLE_DELAY_Init(CM_HRPWM4, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM4, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM4, HRPWM_IDLE_CHA_LVL_LOW);
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM4);  
	
	  HRPWM_IDLE_DELAY_Init(CM_HRPWM5, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM5, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM5, HRPWM_IDLE_CHA_LVL_LOW);
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM5);                                   //enbale delay idle	
	
    HRPWM_IDLE_DELAY_Init(CM_HRPWM6, &pstcIdleDelayInit);                 //
	  HRPWM_IDLE_SetChAIdleLevel(CM_HRPWM6, HRPWM_IDLE_CHA_LVL_LOW);
    HRPWM_IDLE_SetChBIdleLevel(CM_HRPWM6, HRPWM_IDLE_CHA_LVL_LOW);
		HRPWM_IDLE_DELAY_Enable(CM_HRPWM6); 

    /******************DELAY IDLE MODE***********************************/
		HRPWM_IDLE_DELAY_MultiUnitSWTrigger(HRPWM_UNIT_ALL);
}

/**************************************************************
* @brief  BM(burst mode) configuration
*         
*        
* @param  none
* @retval none
***************************************************************/
void HRTIM_BM_Conf(void)
{
		stc_hrpwm_idle_bm_init_t  pstcBMInit;
	  stc_hrpwm_idle_bm_output_init_t pstcBMOutputInit;
		/**********************************************BM Configuration*******************************/
#if HRPWM_BMMODE_ENABLE == 1		

	  HRPWM_IDLE_BM_StructInit(&pstcBMInit);
	
	  pstcBMInit.u32Mode = HRPWM_BM_ACTION_MD2;   //MD2:CMPA = 0;RUN,MD1:CMPA = 0,IDLE
	  pstcBMInit.u32CountSrc  = HRPWM_BM_CNT_SRC_PEROID_POINT_U1;//
	  pstcBMInit.u32CompareValue = 0;             //BM CMP value
	  //pstcBMInit.u32CountPclk0Div = ;
	  pstcBMInit.u32CountReload = HRPWM_BM_CNT_RELOAD_ON; //BM continue mode
	  //pstcBMInit.u32PeriodPoint = HRPWM_CPLT_PERIOD_PEAK; //update source is period
	  pstcBMInit.u32PeriodValue = 25;
	  pstcBMInit.u64TriggerSrc  = HRPWM_BM_TRIG_NONE;
    HRPWM_IDLE_BM_Init(&pstcBMInit);
	
	  HRPWM_IDLE_BM_PeriodBufEnable();
	  HRPWM_IDLE_BM_CompareBufEnable();
		
		
		HRPWM_IDLE_BM_OutputStructInit(&pstcBMOutputInit);
		pstcBMOutputInit.u32Follow = DISABLE;                                //follow enable or disable
		pstcBMOutputInit.u32IdleChAEnterDelay = HRPWM_BM_DELAY_ENTER_CHA_ON; //BM IDLE  is enable
		pstcBMOutputInit.u32IdleChBEnterDelay = HRPWM_BM_DELAY_ENTER_CHB_ON; //BM IDLE  is enable
		pstcBMOutputInit.u32IdleOutputChAStatus = HRPWM_BM_OUTPUT_CHA_ON;    //BM output state depend on 
		pstcBMOutputInit.u32IdleOutputChBStatus = HRPWM_BM_OUTPUT_CHB_ON;    //
		pstcBMOutputInit.u32UnitCountReset = DISABLE;  	                     //BM IDLE counter is reset    
                                       
    HRPWM_IDLE_BM_OutputInit(CM_HRPWM1, &pstcBMOutputInit);
		HRPWM_IDLE_BM_OutputInit(CM_HRPWM2, &pstcBMOutputInit);
		HRPWM_IDLE_BM_OutputInit(CM_HRPWM3, &pstcBMOutputInit);
		
		HRPWM_IDLE_BM_OutputInit(CM_HRPWM4, &pstcBMOutputInit);
		HRPWM_IDLE_BM_OutputInit(CM_HRPWM5, &pstcBMOutputInit);
		HRPWM_IDLE_BM_OutputInit(CM_HRPWM6, &pstcBMOutputInit);
		/*********************************************BM PRD and CMP configuration*********************/
//		MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_EEV8 ,1 << HRPWM_BMSTRG1_EEV8_POS); 		//exrernal EVENT8 enable
//		  MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_EEV7 ,1 << HRPWM_BMSTRG1_EEV7_POS); 		//exrernal EVENT7 enable
//		MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_T4UDFEEV8 ,1 << HRPWM_BMSTRG1_T4UDFEEV8_POS); 		//exrernal EVENT8 enable
//		MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_T4OVFEEV8 ,1 << HRPWM_BMSTRG1_T4OVFEEV8_POS); 		//exrernal EVENT8 enable
//	 	MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_T1UDFEEV7 ,1 << HRPWM_BMSTRG1_T1UDFEEV7_POS); 		//exrernal EVENT7 enable
 //		MODIFY_REG32(CM_HRPWM6->BMSTRG1, HRPWM_BMSTRG1_SSTRG ,1 << HRPWM_BMSTRG1_SSTRG_POS); 		//exrernal EVENT8 enable
 
 
	 //40000/10 = 4000
//	 WRITE_REG32(CM_HRPWM1->BMCMBR, 4000);
//	 WRITE_REG32(CM_HRPWM1->BMCMAR, 4000);
//	 WRITE_REG32(CM_HRPWM1->BMPERBR, 8000);
//	 WRITE_REG32(CM_HRPWM1->BMPERAR, 8000);
	 
	 HRPWM_IDLE_BM_SetPeriodReg(25);
   HRPWM_IDLE_BM_SetPeriodReg_Buf(25);
   HRPWM_IDLE_BM_SetCompareReg(13);
   HRPWM_IDLE_BM_SetCompareReg_Buf(13);
	 
	 HRPWM_IDLE_BM_Enable();
	  
#endif	
}

/**************************************************************
* @brief  EMB  configuration
*         
*        
* @param  none
* @retval none
***************************************************************/
void HRPWM_EMB_Conf(void)
{
	   stc_hrpwm_emb_config_t pstcEmbConfig;
		/* *****************************EMB command ******************************/
		/******PHASE1-LLC********/
	#if SDK_ENABLE == 0
		CLR_REG32_BIT(CM_HRPWM1->PCNAR1, HRPWM_PCNAR1_EMBSA);//EMB通道0~6,只能选择期中的一个通道
		CLR_REG32_BIT(CM_HRPWM1->PCNAR1, HRPWM_PCNAR1_EMBRA);//EMB事件释放方式，ONE SHOT
	  SET_REG32_BIT(CM_HRPWM1->PCNAR1, (3 << HRPWM_PCNAR1_EMBRA_POS) /*HRPWM_PCNAR1_EMBRA_1*/);//EMB事件释放方式，
		SET_REG32_BIT(CM_HRPWM1->PCNAR1, HRPWM_PCNAR1_EMBCA_1);//EMB事件将PWMA端口置低
		
		CLR_REG32_BIT(CM_HRPWM1->PCNBR1, HRPWM_PCNBR1_EMBSB);//EMB通道0
		CLR_REG32_BIT(CM_HRPWM1->PCNBR1, HRPWM_PCNBR1_EMBRB);//EMB事件释放方式，ONE SHOT
		SET_REG32_BIT(CM_HRPWM1->PCNBR1, (3 << HRPWM_PCNAR1_EMBRA_POS));//EMB事件释放方式，
		SET_REG32_BIT(CM_HRPWM1->PCNBR1, HRPWM_PCNBR1_EMBCB_1);//EMB事件将PWMB端口置低
	
	#else
	
	  HRPWM_EMB_StructInit(&pstcEmbConfig);
	
	  pstcEmbConfig.u32ValidCh = HRPWM_EMB_EVT_CH0;             //select EMB0
	  pstcEmbConfig.u32ReleaseMode = HRPWM_EMB_RELEASE_VALLEY;  //release mode  zero
	  pstcEmbConfig.u32PinStatus = HRPWM_EMB_PIN_LOW;           //pin state     low
	  HRPWM_EMB_ChAConfig(CM_HRPWM1, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM1, &pstcEmbConfig);           
	 
	  HRPWM_EMB_ChAConfig(CM_HRPWM5, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM5, &pstcEmbConfig);   
		
		HRPWM_EMB_ChAConfig(CM_HRPWM3, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM3, &pstcEmbConfig);


    pstcEmbConfig.u32ValidCh = HRPWM_EMB_EVT_CH1;             //select EMB1
	  pstcEmbConfig.u32ReleaseMode = HRPWM_EMB_RELEASE_VALLEY;  //release mode  zero
	  pstcEmbConfig.u32PinStatus = HRPWM_EMB_PIN_LOW;           //pin state     low
	
	  HRPWM_EMB_ChAConfig(CM_HRPWM2, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM2, &pstcEmbConfig);           
	 
	  HRPWM_EMB_ChAConfig(CM_HRPWM4, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM4, &pstcEmbConfig);   
		
		HRPWM_EMB_ChAConfig(CM_HRPWM6, &pstcEmbConfig);
	  HRPWM_EMB_ChBConfig(CM_HRPWM6, &pstcEmbConfig);
	#endif	
}


/**************************************************************
* @brief  external event configuration
*         extern 1    ---------->IDLE
*         extern 6    ---------->FAST Output
* @param  prd       : LLC period 
* @param  sr_value  : sr_vaule
* @param  dead_time : deadtime
* @retval none
***************************************************************/
void ExternEventConfig(void)
{
//  uint32_t  u32EEVTSelectIndex = 0;
	stc_hrpwm_evt_config_t pstcEventConfig;
	stc_hrpwm_evt_filter_config_t pstcFilterConfig;
	stc_hrpwm_evt_filter_signal_config_t pstcSignalConfig;
	
#if 0
	#if EEVT_SLECT_MASK  ==  EEVT_MODE_EXTERNPORT	
			u32EEVTSelectIndex = 0;
	#elif EEVT_SLECT_MASK  ==  EEVT_MODE_CMP	
	    u32EEVTSelectIndex = 1;
	#elif EEVT_SLECT_MASK  ==  EEVT_MODE_TIMERX
	    u32EEVTSelectIndex = 2;
	#elif EEVT_SLECT_MASK  ==  EEVT_MODE_ADCCMP
	    u32EEVTSelectIndex = 3;
	#endif
	
	#if EEVT_SLECT_MASK  ==  EEVT_MODE_CMP
	
	SET_REG32_BIT(CM_HRPWM1->GCTLR,0 << 0);			//EE1Src : CMP1
	SET_REG32_BIT(CM_HRPWM1->GCTLR,1 << 2);			//EE2Src : CMP2
	SET_REG32_BIT(CM_HRPWM1->GCTLR,2 << 16);		//EE2Src : CMP3
	SET_REG32_BIT(CM_HRPWM1->GCTLR,0 << 18);	  //EE4Src : CMP1
	SET_REG32_BIT(CM_HRPWM1->GCTLR,1 << 20);		//EE5Src : CMP2
	SET_REG32_BIT(CM_HRPWM1->GCTLR,2 << 22);		//EE6Src : CMP3
	SET_REG32_BIT(CM_HRPWM1->GCTLR,0 << 24);		//EE7Src : CMP1
	SET_REG32_BIT(CM_HRPWM1->GCTLR,1 << 26);		//EE8Src : CMP2
	SET_REG32_BIT(CM_HRPWM1->GCTLR,2 << 28);		//EE9Src : CMP3
	SET_REG32_BIT(CM_HRPWM1->GCTLR,2 << 30);		//EE10Src : CMP1
	#endif
	//event1~5 no filter
	//event 1
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1SRC ,u32EEVTSelectIndex << HRPWM_EECR1_EE1SRC_POS);  //select extern1 sourec 0	
#if EVENT_SATE_MODE == 0
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1SNS ,0 << HRPWM_EECR1_EE1SNS_POS);  //level 
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1POL ,0 << HRPWM_EECR1_EE1POL_POS);  //high
#elif EVENT_SATE_MODE == 1
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1SNS ,1 << HRPWM_EECR1_EE1SNS_POS);  //Up edge 
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1POL ,0 << HRPWM_EECR1_EE1POL_POS);  //high
#elif EVENT_SATE_MODE == 2
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1SNS ,0 << HRPWM_EECR1_EE1SNS_POS);  //level  
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1POL ,1 << HRPWM_EECR1_EE1POL_POS);  //low
#elif EVENT_SATE_MODE == 3
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1SNS ,2 << HRPWM_EECR1_EE1SNS_POS);  //low edge  
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1POL ,1 << HRPWM_EECR1_EE1POL_POS);  //
#endif
  //MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE1FAST ,1 << HRPWM_EECR1_EE1FAST_POS);  //fast dynamic
	
	//event 2
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE2SRC ,u32EEVTSelectIndex << HRPWM_EECR1_EE2SRC_POS);  //select extern1 sourec 0	
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE2SNS ,0 << HRPWM_EECR1_EE2SNS_POS);  //up edge
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE2POL ,0 << HRPWM_EECR1_EE2POL_POS);  //high

  //MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE2FAST ,1 << HRPWM_EECR1_EE2FAST_POS);  //fast dynamic
	
	//event 3
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE3SRC ,u32EEVTSelectIndex << HRPWM_EECR1_EE3SRC_POS);  //select extern1 sourec 0	
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE3SNS ,0 << HRPWM_EECR1_EE3SNS_POS);  //down edge
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE3POL ,0 << HRPWM_EECR1_EE3POL_POS);  //high level
  //MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE3FAST ,1 << HRPWM_EECR1_EE3FAST_POS);  //fast dynamic
	
	//event 4
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE4SRC ,u32EEVTSelectIndex << HRPWM_EECR1_EE4SRC_POS);  //select extern1 sourec 0	
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE4SNS ,0 << HRPWM_EECR1_EE4SNS_POS);  //up edge
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE4POL ,1 << HRPWM_EECR1_EE4POL_POS);  //high level
  //MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE4FAST ,1 << HRPWM_EECR1_EE4FAST_POS);  //fast dynamic

	//event 5
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE5SRC ,u32EEVTSelectIndex << HRPWM_EECR1_EE5SRC_POS);  //select extern1 sourec 0	
	MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE5SNS ,0 << HRPWM_EECR1_EE5SNS_POS);  //up edge
  MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE5POL ,0 << HRPWM_EECR1_EE5POL_POS);  //high level
  //MODIFY_REG32(CM_HRPWM1->EECR1, HRPWM_EECR1_EE5FAST ,1 << HRPWM_EECR1_EE5FAST_POS);  //fast dynamic

  
	//event6~10 filter for IDLE or BM mode(EVENT 7 or EVENT 8)
	//event 6
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6SRC ,u32EEVTSelectIndex << HRPWM_EECR2_EE6SRC_POS);  //select extern1 sourec TRM0-CMPA
#if EVENT_SATE_MODE == 0
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6SNS ,0 << HRPWM_EECR2_EE6SNS_POS);  //level 
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6POL ,0 << HRPWM_EECR2_EE6POL_POS);  //high
#elif EVENT_SATE_MODE == 1
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6SNS ,1 << HRPWM_EECR2_EE6SNS_POS);  //Up edge 
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6POL ,0 << HRPWM_EECR2_EE6POL_POS);  //high
#elif EVENT_SATE_MODE == 2
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6SNS ,0 << HRPWM_EECR2_EE6SNS_POS);  //level  
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6POL ,1 << HRPWM_EECR2_EE6POL_POS);  //low
#elif EVENT_SATE_MODE == 3
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6SNS ,2 << HRPWM_EECR2_EE6SNS_POS);  //low edge  
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE6POL ,1 << HRPWM_EECR2_EE6POL_POS);  //
#endif
 	//event 7	
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE7SRC ,u32EEVTSelectIndex << HRPWM_EECR2_EE7SRC_POS);  //select extern1 sourec 1	
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE7SNS ,0 << HRPWM_EECR2_EE7SNS_POS);  //down dege
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE7POL ,0 << HRPWM_EECR2_EE7POL_POS);  //high level
  //event 8
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8SRC ,u32EEVTSelectIndex << HRPWM_EECR2_EE8SRC_POS);  //select extern1 sourec 1	
#if EVENT_SATE_MODE == 0
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8SNS ,0 << HRPWM_EECR2_EE8SNS_POS);  //level 
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8POL ,0 << HRPWM_EECR2_EE8POL_POS);  //high
#elif EVENT_SATE_MODE == 1
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8SNS ,1 << HRPWM_EECR2_EE8SNS_POS);  //Up edge 
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8POL ,0 << HRPWM_EECR2_EE8POL_POS);  //high
#elif EVENT_SATE_MODE == 2
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8SNS ,0 << HRPWM_EECR2_EE8SNS_POS);  //level  
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8POL ,1 << HRPWM_EECR2_EE8POL_POS);  //low
#elif EVENT_SATE_MODE == 3
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8SNS ,2 << HRPWM_EECR2_EE8SNS_POS);  //low edge  
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE8POL ,1 << HRPWM_EECR2_EE8POL_POS);  //
#endif
  //event 9
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE9SRC ,u32EEVTSelectIndex << HRPWM_EECR2_EE9SRC_POS);  //	
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE9SNS ,0 << HRPWM_EECR2_EE9SNS_POS);  //level mode
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE9POL ,0 << HRPWM_EECR2_EE9POL_POS);  //high level
  //event 10
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE10SRC ,u32EEVTSelectIndex << HRPWM_EECR2_EE10SRC_POS);  //	
	MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE10SNS ,0 << HRPWM_EECR2_EE10SNS_POS);  //level mode
  MODIFY_REG32(CM_HRPWM1->EECR2, HRPWM_EECR2_EE10POL ,1 << HRPWM_EECR2_EE10POL_POS);  //high level


	//fliter select EEVT6~EEVT10
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EEVSD ,1 << HRPWM_EECR3_EEVSD_POS);  //filter clock is fPCLK0/2
#if 1	
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EE6F ,4 << HRPWM_EECR3_EE6F_POS);    //filter times is 6
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EE7F ,2 << HRPWM_EECR3_EE7F_POS);    //filter times is 4
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EE8F ,4 << HRPWM_EECR3_EE8F_POS);    //filter times is 6
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EE9F ,2 << HRPWM_EECR3_EE9F_POS);    //filter times is 4
	MODIFY_REG32(CM_HRPWM1->EECR3, HRPWM_EECR3_EE10F ,2 << HRPWM_EECR3_EE10F_POS);  //filter times is 4
#endif	
	
	//latch/TO/Win/blanking select 
	//event 1 is offsent mode  ----------->PWM output state
#if BlankingLatchEnable == 1
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1LAT ,1 << HRPWM_EEFLTCR1_EE1LAT_POS);  //store fault function is disable
#else
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1LAT ,0 << HRPWM_EEFLTCR1_EE1LAT_POS);  //store fault function is disable
#endif

#if WINDOWM_TimeOut_Enable == 1
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1TMO ,1 << HRPWM_EEFLTCR1_EE1TMO_POS);   //over time disable
#else
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1TMO ,0 << HRPWM_EEFLTCR1_EE1TMO_POS);   //over time disable
#endif
#if BLANKING_Win_Offset_Slt == 0    // [offsent,window]
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 0 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window 
#elif BLANKING_Win_Offset_Slt == 1   //[xxx,offsent]
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 2 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window 	
#elif BLANKING_Win_Offset_Slt == 2   //[xxx,window]
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 3 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window 
#elif BLANKING_Win_Offset_Slt == 3   //UINT2 [offsent,window]
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 4 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window
#elif BLANKING_Win_Offset_Slt == 4   //[offsent,window]
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 14 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window 
#elif BLANKING_Win_Offset_Slt == 5   //UINT2 [offsent,window]
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE1FM , 15 << HRPWM_EEFLTCR1_EE1FM_POS);   //local  offset and window 	
#endif
	//event 2 is offsent mode  ----------->PWM output state
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE2LAT ,0 << HRPWM_EEFLTCR1_EE2LAT_POS);  //store fault function is disable 
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE2TMO ,0 << HRPWM_EEFLTCR1_EE2TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE2FM , 0 << HRPWM_EEFLTCR1_EE2FM_POS);   //local  offset and window
	//event 3 is offsent mode  ----------->PWM output state
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE3LAT ,0 << HRPWM_EEFLTCR1_EE3LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE3TMO ,0 << HRPWM_EEFLTCR1_EE3TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE3FM , 0 << HRPWM_EEFLTCR1_EE3FM_POS);   //local  offset and window 
	//event 4 is window mode  ----------->PWM output state
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE4LAT ,0 << HRPWM_EEFLTCR1_EE4LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE4TMO ,0 << HRPWM_EEFLTCR1_EE4TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE4FM , 0 << HRPWM_EEFLTCR1_EE4FM_POS);   //local  offset and window 
	//event 5 is window mode  ----------->PWM output state
  MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE5LAT ,0 << HRPWM_EEFLTCR1_EE5LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE5TMO ,0 << HRPWM_EEFLTCR1_EE5TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EE5FM , 0 << HRPWM_EEFLTCR1_EE5FM_POS);   //local  offset and window
	//event 6 is window  mode   --------->IDLE
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE6LAT ,0 << HRPWM_EEFLTCR2_EE6LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE6TMO ,0 << HRPWM_EEFLTCR2_EE6TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE6FM , 0 << HRPWM_EEFLTCR2_EE6FM_POS);   //native offset and window 
	//event 7 is window  mode  
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE7LAT ,0 << HRPWM_EEFLTCR2_EE7LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE7TMO ,0 << HRPWM_EEFLTCR2_EE7TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE7FM , 0 << HRPWM_EEFLTCR2_EE7FM_POS);   //native offset and window
	//event 8 is window  mode   
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE8LAT ,0 << HRPWM_EEFLTCR2_EE8LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE8TMO ,0 << HRPWM_EEFLTCR2_EE8TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE8FM , 0 << HRPWM_EEFLTCR2_EE8FM_POS);   //native offset and window
  //event 9 is window  mode  
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE9LAT ,0 << HRPWM_EEFLTCR2_EE9LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE9TMO ,0 << HRPWM_EEFLTCR2_EE9TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE9FM , 0 << HRPWM_EEFLTCR2_EE9FM_POS);   //native offset and window
	//event 10 is window  mode   
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE10LAT ,0 << HRPWM_EEFLTCR2_EE10LAT_POS);  //store fault function is disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE10TMO ,0 << HRPWM_EEFLTCR2_EE10TMO_POS);   //over time disable
	MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR2_EE10FM , 0 << HRPWM_EEFLTCR2_EE10FM_POS);   //native offset and window


  //blanking delay 
	#if BlankingDelay == 1
	SET_REG32_BIT(CM_HRPWM1->GCTLR,1 << 4);
	#endif
  //window/blanking initional level
  MODIFY_REG32(CM_HRPWM1->EEFLTCR2, HRPWM_EEFLTCR1_EEINTPOL ,0 << HRPWM_EEFLTCR1_EEINTPOL_POS);  //Init filter is 0
	
	//offsent and window update
#if 	BlANKING_MODE == 0
	CLR_REG32_BIT(CM_HRPWM1->GCONR1, (1L << 6));   //external event Blanking select   0:mode 1 1:mode 2
#else
  SET_REG32_BIT(CM_HRPWM1->GCONR1, (1L << 6));   //external event Blanking select   0:mode 1 1:mode 2
	#if BLANKING_MODE2_REF == 0
	CLR_REG32_BIT(CM_HRPWM1->GCONR1, (1L << 7));   //external event time reference  0:prd    1:zero
	#else
	SET_REG32_BIT(CM_HRPWM1->GCONR1, (1L << 7));   //external event time reference  0:prd    1:zero
	#endif
#endif

	
	
	
	//intiation configuration
	MODIFY_REG32(CM_HRPWM1->EEFLTCR1, HRPWM_EEFLTCR1_EEINTPOL ,0 << HRPWM_EEFLTCR1_EEINTPOL_POS);  //Init filter is 0
	
	//blanking and window select
	MODIFY_REG32(CM_HRPWM1->EEFOFFSETBR, HRPWM_EEFOFFSETBR_OFFSETDIR ,1 << HRPWM_EEFOFFSETBR_OFFSETDIR_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFOFFSETBR, HRPWM_EEFOFFSETBR_OFFSET ,   3000 << HRPWM_EEFOFFSETBR_OFFSET_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFWINBR,    HRPWM_EEFWINBR_WINDIR ,      1 << HRPWM_EEFWINBR_WINDIR_POS);         //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFWINBR,    HRPWM_EEFWINBR_WIN ,         5000 << HRPWM_EEFWINBR_WIN_POS);        //offsent is counter up
	
	MODIFY_REG32(CM_HRPWM1->EEFOFFSETAR, HRPWM_EEFOFFSETAR_OFFSET ,   3000 << HRPWM_EEFOFFSETAR_OFFSET_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFOFFSETAR, HRPWM_EEFOFFSETAR_OFFSETDIR ,1 << HRPWM_EEFOFFSETAR_OFFSETDIR_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFWINAR,    HRPWM_EEFWINAR_WIN ,         5000 << HRPWM_EEFWINAR_WIN_POS);        //offsent is counter up
	MODIFY_REG32(CM_HRPWM1->EEFWINAR,    HRPWM_EEFWINAR_WINDIR ,      1 << HRPWM_EEFWINAR_WINDIR_POS);         //offsent is counter up
	
	
	MODIFY_REG32(CM_HRPWM2->EEFOFFSETBR, HRPWM_EEFOFFSETBR_OFFSETDIR ,1 << HRPWM_EEFOFFSETBR_OFFSETDIR_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFOFFSETBR, HRPWM_EEFOFFSETBR_OFFSET ,   5000 << HRPWM_EEFOFFSETBR_OFFSET_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFWINBR,    HRPWM_EEFWINBR_WINDIR ,      1 << HRPWM_EEFWINBR_WINDIR_POS);         //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFWINBR,    HRPWM_EEFWINBR_WIN ,         7000 << HRPWM_EEFWINBR_WIN_POS);        //offsent is counter up
	
	MODIFY_REG32(CM_HRPWM2->EEFOFFSETAR, HRPWM_EEFOFFSETAR_OFFSET ,   5000 << HRPWM_EEFOFFSETAR_OFFSET_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFOFFSETAR, HRPWM_EEFOFFSETAR_OFFSETDIR ,1 << HRPWM_EEFOFFSETAR_OFFSETDIR_POS);   //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFWINAR,    HRPWM_EEFWINAR_WIN ,         7000 << HRPWM_EEFWINAR_WIN_POS);        //offsent is counter up
	MODIFY_REG32(CM_HRPWM2->EEFWINAR,    HRPWM_EEFWINAR_WINDIR ,      1 << HRPWM_EEFWINAR_WINDIR_POS);         //offsent is counter up
#else
  /**************************Event port configuration**********************************/
	HRPWM_EVT_StructInit(&pstcEventConfig);
	pstcEventConfig.u32EventSrc = HRPWM_EVT_SRC1;
	pstcEventConfig.u32EventSrc2 = HRPWM_EVT_SRC2_CMP1;
	pstcEventConfig.u32ExtEvtDetect = HRPWM_EVT_GEN_DETECT_ON;  //EEVT port output enable
	pstcEventConfig.u32FastAsyncMode = HRPWM_EVT_FAST_ASYNC_OFF;
	pstcEventConfig.u32FilterClock = HRPWM_EVT_EEVS_PCLK0;
	pstcEventConfig.u32ValidAction = HRPWM_EVT_VALID_LVL;
	pstcEventConfig.u32ValidLevel = HRPWM_EVT_VALID_LVL_HIGH;
  HRPWM_EVT_Config(HRPWM_EVT1, &pstcEventConfig);
	
	/*************************filter configuration**************************************/
	HRPWM_EVT_FilterStructInit(&pstcFilterConfig);
	pstcFilterConfig.u32Mode = HRPWM_EVT_FILTER_MD_BLANK;
	pstcFilterConfig.u32Latch = HRPWM_EVT_FILTER_LATCH_OFF;
	pstcFilterConfig.u32WindowTimeout = HRPWM_EVT_FILTER_TIMEOUT_OFF;
  HRPWM_EVT_FilterConfig(CM_HRPWM1, HRPWM_EVT1, &pstcFilterConfig);
	
  /* Filter signal configuration */
  HRPWM_EVT_FilterSignalStructInit(&pstcSignalConfig);
	pstcSignalConfig.u32InitPolarity = HRPWM_EVT_FILTER_INIT_POLARITY_LOW;
	pstcSignalConfig.u32Offset = 6000;
	pstcSignalConfig.u32OffsetDir = HRPWM_EVT_FILTER_OFS_DIR_UP;
	pstcSignalConfig.u32Window = 15000;
	pstcSignalConfig.u32WindowDir = HRPWM_EVT_FILTER_WIN_DIR_UP;
  HRPWM_EVT_FilterSignalConfig(CM_HRPWM1, &pstcSignalConfig);
	
	HRPWM_EVT_FilterSetOffsetDir_Buf(CM_HRPWM1, HRPWM_EVT_FILTER_OFS_DIR_UP);
	HRPWM_EVT_FilterSetWindowDir_Buf(CM_HRPWM1, HRPWM_EVT_FILTER_WIN_DIR_UP);
	HRPWM_EVT_FilterSetOffset_Buf(CM_HRPWM1, 6000);
	HRPWM_EVT_FilterSetWindow_Buf(CM_HRPWM1,15000);
	
	HRPWM_PWM_ChASetPolarityUpExtEvent(CM_HRPWM1, HRPWM_EVT1, HRPWM_PWM_EXT_EVT_LOW);
#endif	
}



/**************************************************************
* @brief  LLC update period
* @param  prd       : LLC period 
* @param  sr_value  : sr_vaule
* @param  dead_time : deadtime
* @retval none
***************************************************************/
//u32  chy_test_230318 = 0;
void HRPWM_UpdatePRD(LL_Ctrl  *LL_Ctrl_RealTemp)
{
	  //chy_test_230318 = CM_HRPWM1->GBSFLR;
	  int32_t  tempvalue = 0;
//	  int32_t  tempvalue_0 = 0;
//	  int32_t  tempvalue_1 = 0;
//	  static uint32_t  cunter = 0;
		if((CM_HRPWM_COMMON->GBSFLR&0x003f)==0x003f)
		{

			  CLR_REG32_BIT(CM_HRPWM_COMMON->GBCONR,0x003f);//
			
#if HRPWM_COUNTERMODE_SELECT == HRPWM_COUNTERMODE_UPDOWN			

			    //prd update
//				  HRPWM_SetPeriodValue(HRPWM_UNIT_1, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
//					HRPWM_SetPeriodValue(HRPWM_UNIT_2, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
//					HRPWM_SetPeriodValue(HRPWM_UNIT_3, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
//			    HRPWM_SetPeriodValue(HRPWM_UNIT_4, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
//					HRPWM_SetPeriodValue(HRPWM_UNIT_5, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
//					HRPWM_SetPeriodValue(HRPWM_UNIT_6, HRPWM_PERIOD_REG_B,(LL_Ctrl_RealTemp->Prd));
			    tempvalue = LL_Ctrl_RealTemp->Prd;
			    WRITE_REG32(CM_HRPWM1->HRPERBR,((uint32_t)(tempvalue)));
         #if   PWM2_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_NOR			
			    WRITE_REG32(CM_HRPWM2->HRPERBR,((uint32_t)(tempvalue)));
         #endif
			
         #if   PWM3_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_NOR
					WRITE_REG32(CM_HRPWM3->HRPERBR,((uint32_t)(tempvalue)));
         #endif
			
         #if   PWM4_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_NOR			
			
					WRITE_REG32(CM_HRPWM4->HRPERBR,((uint32_t)(tempvalue)));
				 #endif
				 
         #if   PWM5_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_NOR
					WRITE_REG32(CM_HRPWM5->HRPERBR,((uint32_t)(tempvalue)));
				 #endif
				 
         #if   PWM6_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_NOR
					WRITE_REG32(CM_HRPWM6->HRPERBR,((uint32_t)(tempvalue)));
				 #endif
				         
				  tempvalue >>= 1;
					#if   PWM1_MODE_WORK_MODE  == MODE_NORMAL_NOR_MODE
			    WRITE_REG32(CM_HRPWM1->HRGCMCR,((uint32_t)(tempvalue)));
					#endif
					#if   PWM2_MODE_WORK_MODE  == MODE_NORMAL_NOR_MODE
			    WRITE_REG32(CM_HRPWM2->HRGCMCR,((uint32_t)(tempvalue)));
					#endif
					#if   PWM4_MODE_WORK_MODE  == MODE_NORMAL_NOR_MODE
					WRITE_REG32(CM_HRPWM4->HRGCMCR,((uint32_t)(tempvalue)));
					#endif
					#if   PWM5_MODE_WORK_MODE  == MODE_NORMAL_NOR_MODE
			    WRITE_REG32(CM_HRPWM5->HRGCMCR,((uint32_t)(tempvalue)));
					#endif

	        WRITE_REG32(CM_HRPWM3->HRGCMCR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRGCMCR,((uint32_t)(tempvalue)));
								
					/**************dead time update****************************/
			    tempvalue = LL_Ctrl_RealTemp->DeadTime_P1;
			    WRITE_REG32(CM_HRPWM1->HRDTUBR,((uint32_t)(tempvalue)));	
					WRITE_REG32(CM_HRPWM1->HRDTDBR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM2->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM2->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRDTDBR,((uint32_t)(tempvalue)));
					tempvalue = LL_Ctrl_RealTemp->DeadTime_P2;
					WRITE_REG32(CM_HRPWM4->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM4->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM5->HRDTUBR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM5->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRDTDBR,((uint32_t)(tempvalue)));
					
					#if 0
			    /****************shift update******************************/
			    tempvalue = LL_Ctrl_RealTemp->PhaseShift_P1 + HRPWM_LEAST_2xCLOCK;
					//HRPWM_Phase_SetCompareValue(HRPWM_PH_MATCH_IDX1, HRPWM_PH_CMP_REG_B, ((tempvalue)));
					WRITE_REG32(CM_HRPWM1->PHSCMP1B,((uint32_t)(tempvalue)));	
			    tempvalue += LL_Ctrl_RealTemp->PhaseSRShift_P1;
					//HRPWM_Phase_SetCompareValue(HRPWM_PH_MATCH_IDX2, HRPWM_PH_CMP_REG_B, ((tempvalue)));
			    WRITE_REG32(CM_HRPWM1->PHSCMP2B,((uint32_t)(tempvalue)));	
			    //phase 2
			    tempvalue = (LL_Ctrl_RealTemp->Prd >> 1);
			    //HRPWM_Phase_SetCompareValue(HRPWM_PH_MATCH_IDX3, HRPWM_PH_CMP_REG_B, (tempvalue));
					WRITE_REG32(CM_HRPWM1->PHSCMP3B,((uint32_t)(tempvalue)));	
			    tempvalue += LL_Ctrl_RealTemp->PhaseShift_P2 + HRPWM_LEAST_3xCLOCK;
					//HRPWM_Phase_SetCompareValue(HRPWM_PH_MATCH_IDX4, HRPWM_PH_CMP_REG_B, tempvalue);
					WRITE_REG32(CM_HRPWM1->PHSCMP4B,((uint32_t)(tempvalue)));	
			    tempvalue += LL_Ctrl_RealTemp->PhaseSRShift_P2;
			    //HRPWM_Phase_SetCompareValue(HRPWM_PH_MATCH_IDX5, HRPWM_PH_CMP_REG_B, tempvalue);
					WRITE_REG32(CM_HRPWM1->PHSCMP5B,((uint32_t)(tempvalue)));	
					
					#endif
#else
         //prd update
			    tempvalue = LL_Ctrl_RealTemp->Prd;
			    WRITE_REG32(CM_HRPWM1->HRPERBR,((uint32_t)(tempvalue)));
         	WRITE_REG32(CM_HRPWM2->HRPERBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRPERBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM4->HRPERBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM5->HRPERBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRPERBR,((uint32_t)(tempvalue)));
					
				  tempvalue >>= 1;
			    WRITE_REG32(CM_HRPWM1->HRGCMCR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM2->HRGCMCR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRGCMCR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM4->HRGCMCR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM5->HRGCMCR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRGCMCR,((uint32_t)(tempvalue)));

					
					/**************dead time update****************************/
			    tempvalue = LL_Ctrl_RealTemp->DeadTime_P1;
			    WRITE_REG32(CM_HRPWM1->HRDTUBR,((uint32_t)(tempvalue)));	
					WRITE_REG32(CM_HRPWM1->HRDTDBR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM2->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM2->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM3->HRDTDBR,((uint32_t)(tempvalue)));
					tempvalue = LL_Ctrl_RealTemp->DeadTime_P2;
					WRITE_REG32(CM_HRPWM4->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM4->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM5->HRDTUBR,((uint32_t)(tempvalue)));
			    WRITE_REG32(CM_HRPWM5->HRDTDBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRDTUBR,((uint32_t)(tempvalue)));
					WRITE_REG32(CM_HRPWM6->HRDTDBR,((uint32_t)(tempvalue)));
			    /****************shift update******************************/
					#if 0
					//Phase1
			    tempvalue = 128;//(LL_Ctrl_RealTemp->Prd >> 1); 
					tempvalue += LL_Ctrl_RealTemp->PhaseShift_P1 /*+ HRPWM_LEAST_2xCLOCK*/;
					WRITE_REG32(CM_HRPWM1->PHSCMP1B,((uint32_t)(tempvalue)));	
					//Phase1 SR
			    tempvalue += LL_Ctrl_RealTemp->PhaseSRShift_P1;
			    WRITE_REG32(CM_HRPWM1->PHSCMP2B,((uint32_t)(tempvalue)));	
					
			    //phase 2-1
			    tempvalue = (LL_Ctrl_RealTemp->Prd >> 2);
//					tempvalue_1 = tempvalue;
					WRITE_REG32(CM_HRPWM1->PHSCMP3B,((uint32_t)(tempvalue)));	
					//phase 2-2 
			    //tempvalue = LL_Ctrl_RealTemp->Prd * 3 >> 2/* + HRPWM_LEAST_3xCLOCK*/;
//			    if(LL_Ctrl_RealTemp->PhaseShift_P2 >= tempvalue_1)
//					{
//						tempvalue += LL_Ctrl_RealTemp->PhaseShift_P2;
//					}
//					else
					{
						tempvalue += LL_Ctrl_RealTemp->PhaseShift_P2;
					}
					WRITE_REG32(CM_HRPWM1->PHSCMP4B,((uint32_t)(tempvalue)));	
					//phase2 SR
			    tempvalue += LL_Ctrl_RealTemp->PhaseSRShift_P2;
					WRITE_REG32(CM_HRPWM1->PHSCMP5B,((uint32_t)(tempvalue)));	
					#endif

#endif

				  WRITE_REG32(CM_HRPWM_COMMON->GBCONR,0xC000003f);
	  }

	//HRPWM_SWSyncUpdate(0x03F);
}
/**************************************************************
* @brief  IDLE  
* @param  prd       : LLC period 
* @param  workmode  : workmode  0: IDLE 1:DELAYIDLE 2:RUN,3:InitRun
* @retval none
***************************************************************/
//uint32_t *P_SSTAIDLR =  (uint32_t *)(0x4003C000 + 0x03A0);
//uint32_t *P_SSTARUNR1 = (uint32_t *)(0x4003C000 + 0x03A4);
//uint32_t *P_SSTARUNR2 = (uint32_t *)(0x4003C000 + 0x03A8);
//uint32_t *P_SSTADIDLR = (uint32_t *)(0x4003C000 + 0x03AC);
//uint32_t test_chy_0320 = 0;
void IDLE_WorkMode(uint16_t workmode)
{
	  if(workmode == 0)    //IDLE          
		{
			WRITE_REG32(CM_HRPWM_COMMON->SSTAIDLR,((uint32_t)(0x0FFF)));			
		}
		else if(workmode == 1) //delay DLE
		{
#if DELAYIDLE_SR_Mask == DELAYIDLE_SW			
#if DELAYIDLE_SR_SW_MASK == 1
			  WRITE_REG32(CM_HRPWM1->SSTADIDLR,((uint32_t)(0x03F)));
			  SET_REG32_BIT(CM_HRPWM1->SSTADIDLR,1 << 0); 
			  SET_REG32_BIT(CM_HRPWM1->SSTADIDLR,1 << 1);
#else			
			
      MODIFY_REG32(CM_HRPWM1->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //	
      MODIFY_REG32(CM_HRPWM2->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //	
//			MODIFY_REG32(CM_HRPWM3->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //	
//			MODIFY_REG32(CM_HRPWM4->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //	
//			MODIFY_REG32(CM_HRPWM5->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //	
//			MODIFY_REG32(CM_HRPWM6->IDLECR, HRPWM_IDLECR_DLYSTRG ,1 << HRPWM_IDLECR_DLYSTRG_POS);  //		
#endif	
#endif
		}
		else if(workmode == 2) //IDLE to RUN
		{
			  if((READ_REG32(CM_HRPWM1->STFLR2) & 0x03) == 0x3)
			  {
					WRITE_REG32(CM_HRPWM_COMMON->SSTARUNR1,((uint32_t)(0x0FFF)));
				}
		}	
	  else if(workmode == 4) //IDLE to RUN
		{
			  if((READ_REG32(CM_HRPWM_COMMON->SSTARUNR1) & 0x03) == 0x0)
			  {
					#if DELAYIDLE_SSTARUN2_ENABLE == 1
					WRITE_REG32(CM_HRPWM_COMMON->SSTARUNR2,((uint32_t)(0x0FFF)));
					//WRITE_REG32(CM_HRPWM1->SSTAR,0x03F);
					#else
					WRITE_REG32(CM_HRPWM1->SSTARUNR1,((uint32_t)(0x0FFF)));
					#endif
				}			
		}
		else if(workmode == 3)//MCU Reset enter IDLE mode
		{
			WRITE_REG32(CM_HRPWM_COMMON->SSTARUNR2,((uint32_t)(0x0FFF)));
		}
}



/**************************************************************
* @brief  PERIOD Link   
* @param  linkIndex       : PWM link register index
						0:none
						1:register1
						2:register2
						4:register3..

* @retval none
***************************************************************/
void PeriodLinkConfi(uint8_t linkIndex)
{
	
	if(linkIndex & 0x02)
	{
		SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 5 ));
	}
	if(linkIndex & 0x04)
	{
		SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 5 ));
	}
		if(linkIndex & 0x08)
	{
		SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 5 ));
	}
		if(linkIndex & 0x10)
	{
		SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 5 ));
	}
		if(linkIndex & 0x20)
	{
		SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 5 ));
	}

	 //		SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 5 ));
//		SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 4 ));
//		SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 4 ));
				
}
/**************************************************************
* @brief  SCMA_B_Confi   
* @param  linkIndex       : PWM link register index
						0:none
						1:register1
						2:register2
						3:register1 and 2...

* @param  scma_b_select
					0:scma
					1:scmb
          2:scma & scmab

* @param  mode
					0:disable
					1:UP
					2:DOWN
					3:UP/DOWN

* @retval none
***************************************************************/
void SCMA_B_Confi(uint8_t linkIndex,uint8_t scma_b_select,uint8_t mode)
{
	  //CMSA source select
	  //SET_REG32_BIT(CM_HRPWM1->SCMASELR,(1 << 2 ));//OVP
	
	  //unit 1 configuration
		SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 16 ));//SCA UP
		//SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 17 ));//SCA DOWN
	  SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 18 ));//SCB UP
		//SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 19 ));//SCB DOWN
	  
	  

	 //unit2 configuration
//	 	SET_REG32_BIT(CM_HRPWM2>GCONR1,(1 << 16 ));//SCA UP
//		SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 17 ));//SCA DOWN
//	  SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 18 ));//SCB UP
//		SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 19 ));//SCB DOWN
	
	
	  	 //unit3 configuration
//	 	SET_REG32_BIT(CM_HRPWM3>GCONR1,(1 << 16 ));//SCA UP
//		SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 17 ));//SCA DOWN
//	  SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 18 ));//SCB UP
//		SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 19 ));//SCB DOWN
	
	
		 //unit4 configuration
//	 	SET_REG32_BIT(CM_HRPWM4>GCONR1,(1 << 16 ));//SCA UP
//		SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 17 ));//SCA DOWN
//	  SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 18 ));//SCB UP
//		SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 19 ));//SCB DOWN

	 //unit5 configuration
//	 	SET_REG32_BIT(CM_HRPWM5>GCONR1,(1 << 16 ));//SCA UP
//		SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 17 ));//SCA DOWN
//	  SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 18 ));//SCB UP
//		SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 19 ));//SCB DOWN

	 //unit6 configuration
//	 	SET_REG32_BIT(CM_HRPWM6>GCONR1,(1 << 16 ));//SCA UP
//		SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 17 ));//SCA DOWN
//	  SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 18 ));//SCB UP
//		SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 19 ));//SCB DOWN
}

/**************************************************************
* @brief  HalfModeConfi   
* @param  linkIndex       : PWM link register index
						0:none
						1:Unit1
						2:Unit2
						3:Unit3

* @retval none
***************************************************************/
void HalfModeConfi(uint8_t linkIndex)
{
	//linkindex is beyond range[1 6]
//	if((linkIndex > 6) || (linkIndex < 1))
//	{
//		return;
//	}

	
#if   PWM1_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE
	  SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 4 ));//half mode
#endif

#if   PWM2_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE	
    SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 4 ));//half mode	
#endif
	
#if   PWM3_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE	
    SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 4 ));//half mode	
#endif
	
#if   PWM4_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE	
    SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 4 ));//half mode	
#endif

#if   PWM5_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE	
    SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 4 ));//half mode	
#endif

#if   PWM6_MODE_WORK_MODE  == MODE_NORMAL_HALF_MODE	
    SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 4 ));//half mode	
#endif
	
	
	
/*********************************period link******************************/
#if   PWM2_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_LINK
	  SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 5 ));
#endif

#if   PWM3_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_LINK
	  SET_REG32_BIT(CM_HRPWM3->GCONR1,(1 << 5 ));
#endif

#if   PWM4_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_LINK
	  SET_REG32_BIT(CM_HRPWM4->GCONR1,(1 << 5 ));
#endif

#if   PWM5_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_LINK
	  SET_REG32_BIT(CM_HRPWM5->GCONR1,(1 << 5 ));
#endif

#if   PWM6_PERIOD_UPDATE_MODE  == MODE_PERIOD_UPDATE_LINK
	  SET_REG32_BIT(CM_HRPWM6->GCONR1,(1 << 5 ));
#endif

}


/**************************************************************
* @brief  SwapConfi   
* @param  linkIndex       : PWM link register index
						0:none
						1:Unit1
						2:Unit2
						3:Unit3

* @retval none
***************************************************************/
uint32_t  u32ChyTest0601 = 0;
void SwapConfi(uint8_t linkIndex,uint8_t state)
{
	//linkindex is beyond range[1 6]
//	if((linkIndex > 6) || (linkIndex < 1))
//	{
//		return;
//	} 
	
	#if 1
	SET_REG32_BIT(CM_HRPWM2->GCONR1,(3 << 9 ));//swap A and B @zero
	if(state == 0)
	{
	  //SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 3 ));//swap A and B @period
		//SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 3 ));//swap A and B @period
	  //SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 2 ));//swap A and B enable
		SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 2 ));//swap A and B enable
	}
	else
	{
		//CLR_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 2 ));
		CLR_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 2 ));
		
	}
	u32ChyTest0601 = CM_HRPWM1->GCONR1;
	#endif
	
	#if 0
	  if(state == 0)
    {
//			SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 0 ));//swap A and B enable
//			SET_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 1 ));//swap A and B enable
			SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 0 ));//swap A and B enable
			SET_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 1 ));//swap A and B enable
			
		}
		else
		{
//			CLR_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 0 ));
//			CLR_REG32_BIT(CM_HRPWM1->GCONR1,(1 << 1 ));
			CLR_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 0 ));
			CLR_REG32_BIT(CM_HRPWM2->GCONR1,(1 << 1 ));
			//SET_REG32_BIT(CM_HRPWM1->GCONR1,(0 << 1 ));//swap A and B enable	
		}
#endif
}

/**************************************************************
* @brief  BURST MODE test  
* @param  prd       : LLC period 
* @param  workmode  : workmode  0: IDLE 1:DELAYIDLE 2:RUN
* @retval none
***************************************************************/
void BM_WorkMode(uint32_t prd)
{
    ;
}


/**************************************************************
* @name   HWSynchConfi
* @brief  hw trigger timer run.  
* @param  modeselt       :
          1: SCMA
          2: CMPA
          3: CMPB
          4: EXTERN Event
* @retval none
***************************************************************/
void HWSynchRunConfi(uint32_t modeselt)
{
    if(modeselt == 1) //
		{
			SET_REG32_BIT(CM_HRPWM2->HSTAR2,(1 << 22 ));//SCMBR
		}
		else if(modeselt == 2) //CMPA
		{
			SET_REG32_BIT(CM_HRPWM2->HSTAR2,(1 << 10 ));//
		}
		else if(modeselt == 3) //CMPB
		{
			SET_REG32_BIT(CM_HRPWM2->HSTAR2,(1 << 11 ));//
		}
		else if(modeselt == 4) //extern event
		{
			 SET_REG32_BIT(CM_HRPWM1->HSTAR2,(1 << 1 ));//external event 1	
			 SET_REG32_BIT(CM_HRPWM2->HSTAR2,(1 << 1 ));//external event 2			
		}
		else if(modeselt == 5) //HSTAR1 internal event trigger
		{
			//select UNIT1 CMPA act trigger source
			WRITE_REG32(CM_AOS->HRPWM_TRGSEL1,EVT_SRC_TMR6_1_UDF);
			//enable internal event trigger 0,
			SET_REG32_BIT(CM_HRPWM2->HSTAR1,(1 << 9 ));	
		}
		SET_REG32_BIT(CM_HRPWM1->HSTAR1,(1 << 7 ));
		SET_REG32_BIT(CM_HRPWM2->HSTAR1,(1 << 7 ));
}


#if 0
/**************************************************************
* @name   HWSynchUpdateConfi
* @brief  hw trigger timer run.  
* @param  modeselt       :
          1: SCMB(UNIT1)
          2: CMPA(UNIT1)
          3: CMPB(UNIT1)
          4: EXTERN Event8
          5: UVF(UNIT1)
* @retval none
***************************************************************/
void HWSynchUpdateConfi(uint32_t modeselt)
{
    if(modeselt == 1) //
		{
			SET_REG32_BIT(CM_HRPWM2->HUPDR2,(1 << 22 ));//SCMBR
		}
		else if(modeselt == 2) //CMPA
		{
			SET_REG32_BIT(CM_HRPWM2->HUPDR2,(1 << 10 ));//
		}
		else if(modeselt == 3) //CMPB
		{
			SET_REG32_BIT(CM_HRPWM2->HUPDR2,(1 << 11 ));//
		}
		else if(modeselt == 4) //extern event
		{
			 SET_REG32_BIT(CM_HRPWM2->HUPDR2,(1 << 7 ));//external event 8			
		}
		else if(modeselt == 5) //HSTAR1 internal event trigger
		{
			//select UNIT1 CMPA act trigger source
			WRITE_REG32(CM_AOS->TMR6_HTSSR0,EVT_SRC_TMR6_1_UDF);
			//enable internal event trigger 0,
			SET_REG32_BIT(CM_HRPWM2->HUPDR1,(1 << 8 ));	
		}
		SET_REG32_BIT(CM_HRPWM2->HUPDR1,(1 << 7 ));
}
#endif

/**************************************************************
* @name   HWSynchClearConfi
* @brief  hw trigger timer run.  
* @param  modeselt       :
          1: SCMB(UNIT1)
          2: CMPA(UNIT1)
          3: CMPB(UNIT1)
          4: EXTERN Event8
          5: UVF(UNIT1)
* @retval none
***************************************************************/
void HWSynchClearConfi(uint32_t modeselt)
{
#if 0
    if(modeselt == 1) //
		{
			SET_REG32_BIT(HRPWMx->HCLRR2,(1 << 22 ));//SCMBR
		}
		else if(modeselt == 2) //CMPA
		{
			SET_REG32_BIT(HRPWMx->HCLRR2,(1 << 10 ));//
		}
		else if(modeselt == 3) //CMPB
		{
			SET_REG32_BIT(HRPWMx->HCLRR2,(1 << 11 ));//
		}
		else if(modeselt == 4) //extern event
		{
			 SET_REG32_BIT(HRPWMx->HCLRR2,(1 << 0 ));//external event 0
			 //SET_REG32_BIT(HRPWMx->HCLRR2,(1 << 1 ));//external event 1			
		}
		else if(modeselt == 5) //HSTAR1 internal event trigger
		{
			//select UNIT1 CMPA act trigger source
			WRITE_REG32(CM_AOS->TMR6_HTSSR0,EVT_SRC_TMR6_1_UDF);
			//enable internal event trigger 0,
			SET_REG32_BIT(HRPWMx->HCLRR1,(1 << 8 ));	
		}
#endif


    
		//UNIT1
		SET_REG32_BIT(CM_HRPWM1->HCLRR2,(1 << 1));    //external event 2
		//SET_REG32_BIT(CM_HRPWM1->HCLRR2,(1 << 0));    //external event 1
		//UNIT2
		SET_REG32_BIT(CM_HRPWM2->HCLRR2,(1 << 1));    //external event 2
		//UNIT3
//		SET_REG32_BIT(CM_HRPWM3->HCLRR2,(1 << 2));   //external event  3
//		//UNIT4
//		SET_REG32_BIT(CM_HRPWM4->HCLRR2,(1 << 3));   //external event  4
//		//UNIT5
//		SET_REG32_BIT(CM_HRPWM5->HCLRR2,(1 << 4));   //external event  5
//		//UNIT6
//		SET_REG32_BIT(CM_HRPWM6->HCLRR2,(1 << 5));   //external event  6
//		
//		//UNIT1
//		SET_REG32_BIT(CM_HRPWM1->HCLRR2,(1 << 6));    //external event 7
//		//UNIT2
//		SET_REG32_BIT(CM_HRPWM2->HCLRR2,(1 << 7));    //external event 8
//		//UNIT3
//		SET_REG32_BIT(CM_HRPWM3->HCLRR2,(1 << 8));   //external event  9
//		//UNIT4
//		SET_REG32_BIT(CM_HRPWM4->HCLRR2,(1 << 9));   //external event  10

		
	
		SET_REG32_BIT(CM_HRPWM1->HCLRR1,(1 << 7 ));
		SET_REG32_BIT(CM_HRPWM2->HCLRR1,(1 << 7 ));
//		SET_REG32_BIT(CM_HRPWM3->HCLRR1,(1 << 7 ));
//		SET_REG32_BIT(CM_HRPWM4->HCLRR1,(1 << 7 ));
//		SET_REG32_BIT(CM_HRPWM5->HCLRR1,(1 << 7 ));
//		SET_REG32_BIT(CM_HRPWM6->HCLRR1,(1 << 7 ));


}


void HRTIM_Repetive_config(uint16_t select_mode,uint32_t repetive_num)
{
	//SET_REG32_BIT(CM_HRPWM1->VPERR, (1 << 8)); //enable SCMA period
	if(select_mode == HRPWM_REPMODE_DISABLE)
	{
		CLR_REG32_BIT(CM_HRPWM1->VPERR, (0x1F << 16)); //select swtooth period
	}
	else if(select_mode == HRPWM_REPMODE_SAWTOOTH_PRD)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x1 << 16)); //select swtooth period
	}
	else if(select_mode == HRPWM_REPMODE_TRIANGLE_ZERO)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x1 << 16)); //select swtooth period
	}
	else if(select_mode == HRPWM_REPMODE_TRIANGLE_PRD)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x2 << 16)); //select swtooth period
	}
	else if(select_mode == HRPWM_REPMODE_TRIANGLE_ZERO_PRD)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x3 << 16)); //select swtooth period
	}
	else if(select_mode == HRPWM_REPMODE_SCMPA)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x1 << 8)); //
	}
	else if(select_mode == HRPWM_REPMODE_SCMPB)
	{
		SET_REG32_BIT(CM_HRPWM1->VPERR, (0x1 << 9)); //
	}
	
	//period select 
	SET_REG32_BIT(CM_HRPWM1->VPERR, (repetive_num << 18)); //select period	
}

/**********************************************************
 *
 *
 **********************************************************/
void HRTIM_OutputReverseConf(uint16_t modeselect)
{
	if(modeselect == 0)
	{
		CLR_REG32_BIT(CM_HRPWM1->GCONR1, (3 << 0)); //
		SET_REG32_BIT(CM_HRPWM2->GCONR1, (3 << 0)); //
	}
	else if(modeselect == 1)
	{
	  CLR_REG32_BIT(CM_HRPWM1->GCONR1, (3 << 0)); //
		CLR_REG32_BIT(CM_HRPWM2->GCONR1, (3 << 0)); //
	}	
	else if(modeselect == 2)
	{
		SET_REG32_BIT(CM_HRPWM1->GCONR1, (3 << 0)); //
		CLR_REG32_BIT(CM_HRPWM2->GCONR1, (3 << 0)); //
	}
	else if(modeselect == 3)
	{
	  CLR_REG32_BIT(CM_HRPWM1->GCONR1, (3 << 0)); //
		CLR_REG32_BIT(CM_HRPWM2->GCONR1, (3 << 0)); //
	}	
	
}


//uint32_t cmpvalue = 0;
uint16_t cmpcnt = 0;
void  TMR6_IrqHandler(void)
{
	//cmpcnt = (cmpcnt ^ 0x01);
	if((CM_HRPWM_COMMON->GBSFLR&0x0001)==0x0001)
	{
		 CLR_REG32_BIT(CM_HRPWM_COMMON->GBSFLR,0x1);
		 GPIO_TogglePins(GPIO_PORT_D, GPIO_PIN_02);
	}
#if (PWM1_SHADOW_SELECT == SHADOW_UPDATE_SELF_PRD) 
	CLR_REG32_BIT(CM_HRPWM1->STFLR1, (0x1 << 6));//OVF	
#else
	CLR_REG32_BIT(CM_HRPWM1->STFLR1, (0x1 << 7));//UDF	
#endif
	
}

void  TMR6_2_IrqHandler(void)
{
	//cmpcnt = (cmpcnt ^ 0x01);
	if((CM_HRPWM_COMMON->GBSFLR&0x0002)==0x0002)
	{
		 CLR_REG32_BIT(CM_HRPWM_COMMON->GBSFLR,0x2);
		 GPIO_TogglePins(GPIO_PORT_B, GPIO_PIN_09);
	}
#if (PWM2_SHADOW_SELECT == SHADOW_UPDATE_SELF_PRD) || (PWM2_SHADOW_SELECT == SHADOW_UPDATE_UNIT1_FULLSWITCH) 
	CLR_REG32_BIT(CM_HRPWM2->STFLR1, (0x1 << 6));//OVF	
#else
	CLR_REG32_BIT(CM_HRPWM2->STFLR1, (0x1 << 7));//UDF	
#endif
	
}

void TMR6_1_SCmp_Handler(void)
{
	cmpcnt = (cmpcnt ^ 0x01);
	//WRITE_REG32(CM_HRPWM1->HRGCMCR,((uint32_t)(cmpcnt)));
	CLR_REG32_BIT(CM_HRPWM1->STFLR1, (0x1 << 11));//scmpb up
	GPIO_TogglePins(GPIO_PORT_D, GPIO_PIN_02);
}

void Hrtim_Interrupt_Confi(void)
{
	  stc_irq_signin_config_t stcIrqConfig;

#if 1
	#if (PWM1_SHADOW_SELECT == SHADOW_UPDATE_SELF_PRD) 
	  SET_REG32_BIT(CM_HRPWM1->ICONR, (0x1 << 6));//OVF
	  stcIrqConfig.enIntSrc = INT_SRC_TMR6_1_OVF;//
  #else
    SET_REG32_BIT(CM_HRPWM1->ICONR, (0x1 << 7));//UVF
	  stcIrqConfig.enIntSrc = INT_SRC_TMR6_1_UDF;//
  #endif 	
    stcIrqConfig.enIRQn = INT001_IRQn;//
    stcIrqConfig.pfnCallback = &TMR6_IrqHandler;  
    (void)INTC_IrqSignIn(&stcIrqConfig);
    NVIC_SetPriority(stcIrqConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT);
    NVIC_ClearPendingIRQ(stcIrqConfig.enIRQn);
    NVIC_EnableIRQ(stcIrqConfig.enIRQn);
	
	#if (PWM2_SHADOW_SELECT == SHADOW_UPDATE_SELF_PRD) || (PWM2_SHADOW_SELECT == SHADOW_UPDATE_UNIT1_FULLSWITCH) 
	  SET_REG32_BIT(CM_HRPWM2->ICONR, (0x1 << 6));//OVF	
	  stcIrqConfig.enIntSrc = INT_SRC_TMR6_2_OVF;//
  #else
    SET_REG32_BIT(CM_HRPWM2->ICONR, (0x1 << 7));//UVF
		stcIrqConfig.enIntSrc = INT_SRC_TMR6_2_UDF;//
  #endif 

    stcIrqConfig.enIRQn = INT002_IRQn;//
    stcIrqConfig.pfnCallback = &TMR6_2_IrqHandler;  
    (void)INTC_IrqSignIn(&stcIrqConfig);
    NVIC_SetPriority(stcIrqConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT);
    NVIC_ClearPendingIRQ(stcIrqConfig.enIRQn);
    NVIC_EnableIRQ(stcIrqConfig.enIRQn);
#else
	  NVIC_ClearPendingIRQ(TMR6_2_OVF_UDF_IRQn);
    NVIC_SetPriority(TMR6_2_OVF_UDF_IRQn, DDL_IRQ_PRIO_DEFAULT);
    NVIC_EnableIRQ(TMR6_2_OVF_UDF_IRQn);
#endif
}

/*
__STATIC_INLINE void HRPWM_Buf_SetUnitGlobalFlagSrc(CM_HRPWM_TypeDef *HRPWMx, uint32_t u32Src)
{
    DDL_ASSERT(IS_VALID_HRPWM_UNIT(HRPWMx));
    if (CM_HRPWM1 == HRPWMx) {
        DDL_ASSERT(IS_VALID_U1_GLOBAL_BUF_FLAG_SRC(u32Src));
    } else {
        DDL_ASSERT(IS_VALID_U2_6_GLOBAL_BUF_FLAG_SRC(u32Src));
    }
    MODIFY_REG32(HRPWMx->GCONR1, HRPWM_GCONR1_BFSEL, u32Src);
}
*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 

